The present invention relates to a semiconductor memory device of a microprocessor having a virtual memory scheme. More particularly, the present invention relates to a semiconductor memory device having an address translator.
Recently, microprocessors have tended to have more functions and to be integrated at a higher density, and have tended to adopt a virtual memory scheme and to have internal memories such as a cache memory which can store the same data as a part of the data stored in a main memory and can be accessed by a physical address. For example, a principal action of a microprocessor having a virtual memory scheme having an address translator and an internal cache memory is as follows: First, a logical address in the virtual memory space is fed to the address translator which outputs a physical address in the real memory space in correspondence with the logical address, while a tag memory in the cache memory also outputs a physical address of data stored in the cache memory, and the two physical addresses are transmitted to a comparator for comparison. When the two physical addresses coincide, the central processing unit of the microprocessor processes data to be read not from an external memory, but from the internal cache memory, so that the processing of the central processing unit can be made faster. As explained above, in previous semiconductor memory devices, it is generally necessary to simultaneously transmit both output data of the address translator and output data cache tag memory to the same functional block or to a comparator.
As the clock frequency of a microprocessor increases, it becomes more and more necessary to make the above-mentioned processing faster. In previous microprocessors, the processing speed is increased by making the processing speeds of the functional blocks, such as the address translator and the cache memories, faster.
In the microprocessors mentioned above, the address translator and the other memories are regarded as independent functional blocks, and the actual structure and floor plan arrangement of these function blocks are such that they are separated from each other. Therefore, it is necessary to simultaneously transmit data output by such function blocks to a distant functional block or a comparator. Thus, even if the function block for data to be transmitted is located near either the address translator or the tag memory of the cache memory, it is necessary to perform data transmittance at least for a distance from the address translator or the tag memory to the functional block, and the transmittance time is one of the factors which prevents making the processing faster.